SPICE Model
PDK
Standard Cell
Advanced High Performance FastSPICE Simulator
Breakthrough FastSPICE algorithm, intelligent topology recognition & automated partition technology
Event-driven architecture with enhanced MT scalability, post-layout circuit topology optimization
Straight-forward usability based on circuit types
Empowered by the advanced infrastructure
Supports 3D-IC and multi-technology simulation including in back-annotation flow
Event driven with better MT scalability
Post layout and RC further optimization
Superior analog accuracy and
digital performance with adaptive dual-solver
One stop solution
from block level to full chip circuit simulation
Advanced infrastructure and
efficient output system to minimize cost
2 billion elements
Circuit detection and auto-partitioning
empowered by ML/AI
Flash/DRAM/SRAM
function verification,
timing & power dissipation
SRAM
characterization
Custom digital
full chip simulation
(CLK Tree, MCU)
SoC
full chip simulation
(Transceiver, Display, CIS, PMIC, etc.)
